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W152
Spread AwareTM, Eight Output Zero Delay Buffer
Features
* Spread AwareTM--designed to work with SSFTG reference signals * Two banks of four outputs each * Configuration options to halve, double, or quadruple the reference frequency refer to Table 1 to determine the specific option which meets your multiplication needs * Outputs may be three-stated * Available in 16-pin SOIC package * Extra strength output drive available (-11/-12 versions) * Contact factory for availability information on 16-pin TSSOP Output to Output Skew: Between Banks ..................... 215 ps Output to Output Skew: Within Banks (Refer to Figure 4) ...................................................100 ps Total Timing Budget Impact: ........................................ 555 ps Max. Phase Error Variation: ......................................225 ps Tracking Skew:...........................................................130 ps Table 1. Configuration Options Device W152-1/11 W152-2/12 W152-3 W152-3 W152-4
[1]
Feedback Signal QA0:3 or QB0:3 QA0:3 QB0:3 QA0:3 QB0:3 QA0:3 or QB0:3
QA0:3 REFx1 REFx1 REFx2 REFx2 REFx4 REFx2
QB0:3 REFx1 REF/2 REFx1 REFx1 REFx2 REFx2
W152-2/12[2]
[2]
Key Specifications
Operating Voltage: ............................................... 3.3V10% Operating Range: .................... 15 MHz < fOUTQA < 140 MHz Cycle-to-Cycle Jitter: (Refer to Figure 3) .................... 225 ps Cycle-to-Cycle Jitter: Frequency Range 25 to140 MHz ......................................................... 125 ps
Notes: 1. W152-11 has stronger output drive than the W152-1. 2. W152-12 has stronger output drive than the W152-2.
Block Diagram
(present on the -3 and -4 only)
Pin Configuration
FBIN REF
/2
PLL
MUX QA0 QA1 QA2
REF QA0 QA1 VDD GND QB0 QB1 SEL1
QB0 QB1
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
FBIN QA3 QA2 VDD GND QB3 QB2 SEL0
SEL0 QA3 /2 SEL1
(present on the -2, -12, and -3 only)
QB2 QB3
Spread Aware is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 June 14, 2000, rev. *B
W152
Pin Definitions
Pin Name REF FBIN Pin No. 1 16 Pin Type I I Pin Description Reference Input: The output signals QA0:3 through QB0:3 will be synchronized to this signal unless the device is programmed to bypass the PLL. Feedback Input: When programmed to zero delay buffer mode, this input must be fed by one of the outputs (QA0:3 or QB0:3) to ensure proper functionality. If the trace between FBIN and the output pin being used for feedback is equal in length to the traces between the outputs and the signal destinations, then the signals received at the destinations will be synchronized to the REF signal input. Outputs from Bank A: The frequency of the signals provided by these pins is determined by the feedback signal connected to FBIN, and the specific W152 option being used. See Table 2. Outputs from Bank B: The frequency of the signals provided by these pins is determined by the feedback signal connected to FBIN, and the specific W152 option being used. See Table 2. Power Connections: Connect to 3.3V. Use ferrite beads to help reduce noise for optimal jitter performance. Ground Connections: Connect all grounds to the common system ground plane. Function Select Inputs: Tie to VDD (HIGH, 1) or GND (LOW, 0) as desired per Table 2.
QA0:3
2, 3, 14, 15
O
QB0:3
6, 7, 10, 11
O
VDD GND SEL0:1
4, 13 5, 12 9, 8
P G I
Overview
The W152 products are eight-output zero delay buffers. A Phase-Locked Loop (PLL) is used to take a time-varying signal and provide eight copies of that same signal out. The external feedback to the PLL provides outputs in phase with the reference inputs. Internal dividers exist in some options allowing the user to get a simple multiple (/2, x2, x4) of the reference input, for details see Table 1. Because the outputs are separated into two banks, it is possible to provide some combination of these multiples at the same time.
Functional Description
Logic inputs provide the user the ability to turn off one or both banks of clocks when not in use, as described in Table 2. Disabling a bank of unused outputs will reduce jitter and power consumption, and will also reduce the amount of EMI generated by the W152. These same inputs allow the user to bypass the PLL entirely if so desired. When this is done, the device no longer acts as a zero delay buffer, it simply reverts to a standard eight-output clock driver. The W152 PLL enters an auto power-down mode when there are no rising edges on the REF input. In this mode, all outputs are three-stated and the PLL is turned off. Table 2. Input Logic SEL1 0 0 1 1 SEL0 0 1 0 1 QA0:3 Active Active Active QB0:3 Three-State Active Active PLL Shutdown Active, Utilized Shutdown, Bypassed Active, Utilized
Spread Aware
Many systems being designed now utilize a technology called Spread Spectrum Frequency Timing Generation. Cypress has been one of the pioneers of SSFTG development, and we designed this product so as not to filter off the Spread Spectrum feature of the Reference input, assuming it exists. When a zero delay buffer is not designed to pass the SS feature through, the result is a significant amount of tracking skew which may cause problems in systems requiring synchronization. For more details on Spread Spectrum timing technology, please see the Cypress application note titled, "EMI Suppression Techniques with Spread Spectrum Frequency Timing Generator (SSFTG) ICs."
Three-State Three-State
2
W152
1 2 3
Ref In QA0 QA1 Power Ground QB0 QB1 SEL1
FB In QA3 QA2 Power Ground QB3 QB2 SEL0
16 15 14 13 12 11 10 9
See Note 3
VDD 0.1 F 10 F
Ferrite Bead 3.3V Supply
VDD
0.1 F
4 5 6 7
VDD or GND (for desired operation mode)
8
VDD or GND (for desired operation mode)
Figure 1. Schematic[3]
Note: 3. Pin 16 needs to be connected to one of the outputs from either bank A or bank B, it should not be connected to both. Pins 2 and 10 are shown here as examples. None of the outputs should be considered aas preferred for the feedback path.
How to Implement Zero Delay
Typically, zero delay buffers (ZDBs) are used because a designer wants to provide multiple copies of a clock signal in phase with each other. The whole concept behind ZDBs is that the signals at the destination chips are all going HIGH at the same time as the input to the ZDB. In order to achieve this, layout must compensate for trace length between the ZDB and the target devices. The method of compensation is described below. External feedback is the trait that allows for this compensation. The PLL on the ZDB will cause the feedback signal to be in phase with the reference signal. When laying out the board, match the trace lengths between the output being used for feedback and the FBIN input to the PLL. If it is desirable to either add a little delay, or slightly precede the input signal, this may also be affected by either making the trace to the FBIN pin a little shorter or a little longer than the traces to the devices being clocked.
some other device. This implementation can be applied to any device (ASIC, multiple output clock buffer/driver, etc.) which is put into the feedback path. Referring to Figure 2, if the traces between the ASIC/buffer and the destination of the clock signal(s) (A) are equal in length to the trace between the buffer and the FBIN pin, the signals at the destination(s) device will be driven HIGH at the same time the Reference clock provided to the ZDB goes HIGH. Synchronizing the other outputs of the ZDB to the outputs form the ASIC/Buffer is more complex however, as any propagation delay in the ASIC/Buffer must be accounted for.
Reference Signal Feedback Input
Zero Delay Buffer
ASIC/ Buffer
A
Inserting Other Devices in Feedback Path
Figure 2. 6 Output Buffer in the Feedback Path Another nice feature available due to the external feedback is the ability to synchronize signals up to the signal coming from
3
W152
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions
.
above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Rating -0.5 to +7.0 -65 to +150 0 to +70 -55 to +125 0.5 Unit V C C C W
Parameter VDD, VIN TSTG TA TB PD
Description Voltage on any pin with respect to GND Storage Temperature Operating Temperature Ambient Temperature under Bias Power Dissipation
DC Electrical Characteristics: TA =0C to 70C, VDD = 3.3V 10%
Parameter IDD VIL VIH VOL VOH IIL IIH Description Supply Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Low Current Input High Current IOL = 12 mA (-11, -12) IOL = 8 mA (-1, -2, -3, -4) IOH = 12 mA (-11, -12) IOH = 8 mA (-1, -2, -3, -4) VIN = 0V VIN = VDD 2.4 50 50 2.0 0.4 Test Condition Unloaded, 100 MHz Min. Typ. Max. 40 0.8 Unit mA V V V V A A
AC Electrical Characteristics: TA = 0C to +70C, VDD = 3.3V 10%
Parameter fIN fOUT tR tF tICLKR tICLKF tPD tSK tD tLOCK tJC Description Input Frequency Output Frequency Output Rise Time (-1, -2, -3, -4) Output Rise Time (-11, -12) Output Fall Time (-1, -2, -3, -4) Output Rise Time (-11, -12) Input Clock Rise Time Input Clock Fall Time FBIN to REF Skew Duty Cycle PLL Lock Time Jitter, Cycle-to-Cycle
[4] [4]
Test Condition Note 3 15-pF load[8] 0.8V to 0.8V, 15-pF load 0.8V to 0.8V, 15-pF load 2.0V to 0.8V, 15-pF load 2.0V to 0.8V, 20-pF load
Min. 15 15
Typ.
Max. 140 140
Unit MHz MHz ns ns ns ns ns ns ps ps % ms ps
2 2
2.5 1.5 2.5 1.5 4.5 4.5 350
[5, 6]
Output to Output Skew
All outputs loaded equally[10] 15-pF load Note 9
[7, 8]
215 45 50 55 1.0 225
Power supply stable
Notes: 3. Input frequency is limited by output frequency range and input to output frequency multiplication factor (which is determined by circuit configuration). See Table 1. 4. Longer input rise and fall time will degrade skew and jitter performance. 5. All AC specifications are measured with a 50 transmission line. 6. Skew is measured at VDD/2 on rising edges. 7. Duty cycle is measured at VDD/2. 8. For the higher drive -11 and -12, the load is 20 pF. 9. For frequencies above 25 MHz CY - CY = 125 ps. 10. Measured across all outputs. Maximum skew between outputs in the same bank is 100 ps.
4
W152
W152 -01 CYCLE - CYCLE JITTER @ 15 pF
1000 900 800 700 600 500 400 300 200 100 0 0 20 40 60 80 100 120 140 160 FREQUENCY in MHz
07/21/99 W152-a1
ps
Figure 3. Cycle to Cycle Jitter at 15 pF
W152 -01 PIN- PIN SKEW @ 15 pF
300 200 100 ps 0 A1 -100 -200 OUTPUT #
PIN A1 = REF O7/21/99 a3
A2
A3
A4
B1
B2
B3
B4
Figure 4. Pin to Pin Skew at 15 pF
Ordering Information
Ordering Code W152 Option -1, -11, -2, -12, -3, -4 G X Package Name Package Type 16-pin SOIC (150 mil) 16-pin TSSOP (4.4 mm)
Document #: 38-00786-*B
5
W152
Package Diagrams
16-Pin Small Outline Integrated Circuit (SOIC, 150 mils)
6
W152
Package Diagrams (continued)
16-Pin Thin Shrink Small Outline Package (TSSOP, 4.4 mm)
(c) Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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